Improvements in the reliability of a silicon carbide semiconductor device have been actively studied in the use of such a semiconductor device, i.e., a semiconductor device including a silicon carbide (SiC) layer, as a power semiconductor device.
Since SiC per se has high strength against dielectric breakdown, the silicon carbide semiconductor device tends to involve dielectric breakdown not in the SiC layer, but in an insulating film disposed on the upper surface of the SiC layer. Hence, preventing the deterioration of the insulating film is important to enhance the reliability of the silicon carbide semiconductor device.
In particular, a silicon carbide semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), that has an insulating gate structure, desirably prevents dielectric breakdown in a gate insulating film.
A SiC-MOSFET or an IGBT, a practical power semiconductor device, typically includes p-type well regions adjacent to each other via a drift layer of n-type. The drift layer has a region sandwiched between the well regions. This region is called a junction field effect transistor (JFET).
A high electric field is applied to a gate insulating film immediately on the JFET region while the MOSFET or the IGBT is OFF. Thus, the gate insulating film tends to involve dielectric breakdown particularly on the JFET region. Accordingly, preventing the dielectric breakdown is under study.
In one example, Japanese Patent Application Laid-Open No. 2011-060930 (Patent Document 1) describes a p− region disposed between p well regions facing each other, via an n− layer. That is, the p− region is formed under a gate insulating film in a JFET region.
Hence, depletion in the upper part of the JFET region is promoted while a MOSFET is OFF. This lowers the electric field strength applied to the gate insulating film in the upper part of the JFET region when compared to a structure provided with no p region. Consequently, the gate insulating film is prevented from breakdown when a high voltage is applied across an element, thereby improving the reliability of the gate insulating film.
In another example, Japanese Patent Application Laid-Open No. 2011-211020 (Patent Document 2) describes p body regions adjacent to each other that are provided with p− regions serving as electric-field reduction layers.
In another example, Japanese Patent Application Laid-Open No. 2015-216348 (Patent Document 3) describes that a threading dislocation in a JFET region of a SiC layer particularly tends to cause dielectric breakdown. Accordingly, an electric-field reduction region of p-type conductivity for electric field reduction is disposed in only a region having a threading dislocation in a surface of a drift layer. This positively reduces the electric field concentration at a portion where breakdown is most likely to occur, thus improving the reliability.